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Rok Krajnc

rkrajnc

Slovenia
Commits
564
Repos
11
Lines of code
3686304
Following
0
2
Overview
11 repos
Last updated: 2018/11/27 — 10:11:00
3
Languages
11 repos
Last updated: 2018/11/27 — 10:11:00
Verilog
 
Commits:
549
LOC:
3388714
C
 
Commits:
324
LOC:
213259
Assembly
 
Commits:
261
LOC:
48629
Python
 
Commits:
183
LOC:
4318
DOS Batch
 
Commits:
39
LOC:
71
Shell
 
Commits:
33
LOC:
379
4
Technologies
11 repos
Last updated: 2018/11/27 — 10:11:00
Image Processing
20 commits
5
Fun facts
11 repos
Last updated: 2018/11/27 — 10:11:00

I'm most productive on

Mondays
14% of users
Mo

I'm most productive during

daytime
49% of users
d

I prefer

snake_case

for naming variables

I prefer

tabs

for indentation

I prefer

list comprehensions

I've used

C for 2 years

I've used

Python for 1 year

I've used

Assembly for 2 years
6
Repositories
11 repos
Last updated: 2018/11/27 — 10:11:00
#
Repository
Commits
Team
Language
Timeline
2
minimig-mist
170
3
Verilog
Minimig for the MiST board
3
minimig-upstream
20
1
Verilog
4
qsoc
13
1
Verilog
5
or1200-qmem
11
1
Verilog
OR1200 - Openrisc 1200 soft-core CPU from opencores.org with added external QMEM bus.
6
minimig-mist
10
3
Verilog
Minimig for the MiST board
7
minimig-upstream
7
1
Verilog
Minimig
8
minsoc
3
6
Verilog
minsoc from opencores.net
9
gideonz_1541ultimate
2
1
C
10
netsid
2
1
Python
SID chip
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