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Rok Krajnc

rkrajnc

Slovenia
Member
00004239
Commits
447
Repos
10
Lines of code
155807
Followers: 0
Following: 0
2
Overview
10 repos
Last updated: 2018/04/09 — 15:04:00
3
Languages
10 repos
Last updated: 2018/04/09 — 15:04:00
Verilog
 
Commits:
434
LOC:
93022
C
 
Commits:
241
LOC:
49675
Assembly
 
Commits:
192
LOC:
7801
Python
 
Commits:
144
LOC:
1980
Shell
 
Commits:
21
LOC:
116
DOS Batch
 
Commits:
12
LOC:
23
4
Technologies
10 repos
Last updated: 2018/04/09 — 15:04:00
Image Processing
16 commits
5
Fun facts
10 repos
Last updated: 2018/04/09 — 15:04:00

I'm most productive on

Mondays
14% of users
Mo

I'm most productive during

daytime
49% of users
d

I prefer

snake_case

for naming variables

I prefer

tabs

for indentation

I prefer

list comprehensions

I`m a

Top Python Developer

I`m a

Top Assembly Developer

I`m a

Top C Developer
6
Repositories
10 repos
Last updated: 2018/04/09 — 15:04:00
#
Repository
Commits
Team
Language
Timeline
2
minimig-mist
170
3
Verilog
3
minimig-upstream
20
1
Verilog
4
qsoc
13
1
Verilog
5
or1200-qmem
11
1
Verilog
6
minimig-mist
10
3
Verilog
7
minimig-upstream
7
1
Verilog
8
minsoc
3
6
Verilog
9
netsid
2
1
Python
10
PlusToo
1
1
Verilog