Create your Sourcerer profile
Start
1
rkrajnc
Slovenia
Member
00004239
Commits
447
Repos
10
Lines of code
155807
Follow
Followers: 0
Following: 0
Follow
2
Overview
3
Languages
Verilog
Commits:
434
LOC:
93022
C
Commits:
241
LOC:
49675
Assembly
Commits:
192
LOC:
7801
Python
Commits:
144
LOC:
1980
Shell
Commits:
21
LOC:
116
DOS Batch
Commits:
12
LOC:
23
4
Technologies
Image Processing
16 commits
5
Fun facts
I'm most productive on
Mondays
14% of users
Mo
I'm most productive during
daytime
49% of users
d
I prefer
snake_case
for naming variables
I prefer
tabs
for indentation
I prefer
list comprehensions
I`m a
Top Python Developer
Ranked higher than
82% of users
82% of users
Based on number of commits
I`m a
Top Assembly Developer
Ranked higher than
97% of users
97% of users
Based on number of commits
I`m a
Top C Developer
Ranked higher than
96% of users
96% of users
Based on number of commits
6
Repositories
#
Repository
Commits
Team
Language
Timeline
1
minimig-de1 
325
1
Verilog
2
minimig-mist
170
3
Verilog
3
minimig-upstream
20
1
Verilog
4
qsoc
13
1
Verilog
5
or1200-qmem
11
1
Verilog
6
minimig-mist
10
3
Verilog
7
minimig-upstream
7
1
Verilog
8
minsoc
3
6
Verilog
9
netsid
2
1
Python
10
PlusToo
1
1
Verilog